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* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF40161B MSI 4-bit synchronous binary counter with asynchronous reset
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
4-bit synchronous binary counter with asynchronous reset
DESCRIPTION The HEF40161B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0 to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count enable trickle (CET)), buffered outputs from all four bit positions (O0 to O3) and a terminal count output (TC). Operation is fully synchronous (except for the MR input) and occurs on the LOW to HIGH transition of CP. When PE is LOW, the next LOW to HIGH transition of CP loads data into the counter from P0 to P3 regardless of the levels of CEP and CET inputs.
HEF40161B MSI
When PE is HIGH, the next LOW to HIGH transition of CP advances the counter to its next state only if both CEP and CET are HIGH; otherwise, no change occurs in the state of the counter. TC is HIGH when the state of the counter is 15 (O1 to O3 = HIGH) and when CET is HIGH. A LOW on MR sets all outputs (O0 to O3 and TC) LOW, independent of the state of all other inputs. Multistage synchronous counting is possible without additional components by using a carry look-ahead counting technique; in this case, TC is used to enable successive cascaded stages. CEP, CET and PE must be stable only during the set-up time before the LOW to HIGH transition of CP.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
January 1995
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4-bit synchronous binary counter with asynchronous reset HEF40161B MSI
Philips Semiconductors
Product specification
4-bit synchronous binary counter with asynchronous reset
PINNING PE P0 to P3 CEP CET CP MR O0 to O3 TC Fig.3 Pinning diagram. parallel enable input parallel data inputs
HEF40161B MSI
count enable parallel input count enable trickle input clock input (LOW to HIGH, edge-triggered) master reset input (active LOW) parallel outputs terminal count output
HEF40161BP(N): 16-lead DIL; plastic (SOT38-1) HEF40161BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF40161BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America SYNCHRONOUS MODE SELECTION PE L H H H Notes 1. MR = HIGH 2. H = HIGH state (the more positive voltage) 3. L = LOW state (the less positive voltage) 4. X = state is immaterial CEP X L X H CET X X L H preset no change no change count Note 1. TC = CET . O0 . O1 . O2 . O3 MODE TERMINAL COUNT GENERATION CET L L H H (O0 O1 O2 O3) L H L H TC L L L H
Fig.4 State diagram.
January 1995
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Philips Semiconductors
Product specification
4-bit synchronous binary counter with asynchronous reset
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1 200 fi + (foCL) x VDD2 5 600 fi + (foCL) x VDD
2
HEF40161B MSI
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
16 000 fi + (foCL) x VDD2
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH CP TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CET TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW MR TC HIGH to LOW 10 15 5 10 15 5 10 15 tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL 110 45 30 115 45 35 130 55 35 140 55 40 105 50 35 90 35 25 120 50 35 145 60 45 220 90 60 230 95 65 260 105 75 280 115 80 210 100 75 185 70 50 245 100 70 295 120 85 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 83 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 88 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 103 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 113 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 78 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 63 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 93 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 118 ns + (0,55 ns/pF) CL 49 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA
January 1995
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Philips Semiconductors
Product specification
4-bit synchronous binary counter with asynchronous reset
VDD V Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL SYMBOL MIN. TYP. 60 30 20 60 30 20 MAX. 120 60 40 120 60 40 ns ns ns ns ns ns
HEF40161B MSI
TYPICAL EXTRAPOLATION FORMULA 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Minimum clock pulse width; LOW Minimum MR pulse width; LOW Recovery time for MR Set-up times Pn CP 5 10 15 5 10 15 5 10 15 5 10 15 5 PE CP 10 15 5 CEP, CET CP Hold times Pn CP 10 15 5 10 15 5 PE CP 10 15 5 CEP, CET CP 10 15 thold thold thold tsu tsu tsu tRMR tWMRL tWCPL SYMBOL MIN. 100 40 30 100 40 30 25 15 10 110 40 30 120 40 25 260 100 70 20 10 5 15 5 5 25 15 10 TYP. 50 20 15 50 20 15 0 0 0 55 20 15 60 20 10 130 50 35 -35 -10 -10 -45 -15 -10 -105 -35 -25 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns see also waveforms Figs 5, 6, 7 and 8
January 1995
6
Philips Semiconductors
Product specification
4-bit synchronous binary counter with asynchronous reset
VDD V Maximum clock pulse frequency 5 10 15 fmax SYMBOL MIN. 2,5 7 9 TYP. 5 14 18 MAX. MHz MHz MHz
HEF40161B MSI
Conditions PE = LOW P0 to P3 = HIGH
Fig.5
Waveforms showing minimum CP and MR pulse widths and MR to CP recovery time.
Condition: PE = MR = HIGH.
Fig.6
Waveforms showing set-up times and hold times for CEP and CET inputs.
January 1995
7
Philips Semiconductors
Product specification
4-bit synchronous binary counter with asynchronous reset
HEF40161B MSI
Conditions PE = LOW MR = HIGH
Fig.7 Waveforms showing set-up times and hold times for Pn inputs.
Condition MR = HIGH
Fig.8 Waveforms showing set-up times and hold times for PE input.
Note Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 8
Philips Semiconductors
Product specification
4-bit synchronous binary counter with asynchronous reset
HEF40161B MSI
Fig.9 Timing diagram.
APPLICATION INFORMATION An example of an application for the HEF40161B is: * Programmable binary counter.
January 1995
9
Philips Semiconductors
Product specification
4-bit synchronous binary counter with asynchronous reset
HEF40161B MSI
NOTE On the TC outputs, glitches can occur during counting. In totally synchronous mode they will not have any adverse affect. However the TC output in asynchronous mode can cause problems.
Fig.10 Synchronous multi-stage counting scheme.
January 1995
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